Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

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Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

20 August 2024

Christopher Batten

Brucek Khailany

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Papers citing "Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation"

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Title
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding Zeng Wang Minghao Shao M. Nabeel P. Roy Likhitha Mankali Jitendra Bhandari Ramesh Karri Ozgur Sinanoglu Muhammad Shafique J. Knechtel 156 1 0 17 Mar 2025
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool Chia-Tung Ho Haoxing Ren Brucek Khailany 87 25 0 15 Aug 2024
LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation Zixi Zhang Greg Chadwick Hugo McNally Yiren Zhao Robert D. Mullins Jianyi Cheng Robert Mullins Yiren Zhao 93 24 0 06 Oct 2023
VeriGen: A Large Language Model for Verilog Code Generation Shailja Thakur Baleegh Ahmad Hammond Pearce Benjamin Tan Brendan Dolan-Gavitt Ramesh Karri S. Garg 97 168 0 28 Jul 2023
Program Synthesis with Large Language Models Jacob Austin Augustus Odena Maxwell Nye Maarten Bosma Henryk Michalewski ... Ellen Jiang Carrie J. Cai Michael Terry Quoc V. Le Charles Sutton ELM AIMat ReCod ALM 203 2,004 0 16 Aug 2021