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OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection
23 July 2024
Fan Cui
Chenyang Yin
Kexing Zhou
You-lin Xiao
Guangyu Sun
Qiang Xu
Qipeng Guo
Demin Song
Dahua Lin
Xingcheng Zhang
Yun
Yun Liang
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Papers citing
"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection"
6 / 6 papers shown
Title
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
Haiyan Qin
Zhiwei Xie
Jingjing Li
Liangchen Li
Xiaotong Feng
Jing Liu
Wang Kang
OffRL
LRM
379
1
0
20 Apr 2025
RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts
Armin Abdollahi
M. Kamal
Massoud Pedram
MoE
393
1
0
27 Mar 2025
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
Zeng Wang
Minghao Shao
M. Nabeel
P. Roy
Likhitha Mankali
Jitendra Bhandari
Ramesh Karri
Ozgur Sinanoglu
Muhammad Shafique
J. Knechtel
127
1
0
17 Mar 2025
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
Mingjie Liu
Yun-Da Tsai
Wenfei Zhou
Haoxing Ren
SyDa
3DV
85
14
0
19 Sep 2024
A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Enrique Dehaerne
Bappaditya Dey
S. Halder
S. de Gendt
67
10
0
26 Apr 2023
LoRA: Low-Rank Adaptation of Large Language Models
J. E. Hu
Yelong Shen
Phillip Wallis
Zeyuan Allen-Zhu
Yuanzhi Li
Shean Wang
Lu Wang
Weizhu Chen
OffRL
AI4TS
AI4CE
ALM
AIMat
371
10,273
0
17 Jun 2021
1