VeriGen: A Large Language Model for Verilog Code Generation

28 July 2023

Papers citing "VeriGen: A Large Language Model for Verilog Code Generation"

26 / 26 papers shown

Title
Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors Nicolas Dupuis Ravi Nair Shyam Ramji Sean McClintock Nishant Chauhan Priyanka Nagpal Bart Blaner Ken Valk Leon Stok Ruchir Puri 24 0 0 14 May 2025
LATENT: LLM-Augmented Trojan Insertion and Evaluation Framework for Analog Netlist Topologies Jayeeta Chaudhuri Arjun Chaudhuri Krishnendu Chakrabarty 28 0 0 09 May 2025
Deep Representation Learning for Electronic Design Automation Pratik Shrestha Saran Phatharodom Alec Aversa David Blankenship Zhengfeng Wu Ioannis Savidis 22 0 0 04 May 2025
LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs Baleegh Ahmad Hammond Pearce Ramesh Karri Benjamin Tan 39 0 0 30 Apr 2025
LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning Neha Prakriya Zijian Ding Yizhou Sun Jason Cong 33 0 0 29 Apr 2025
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence Haiyan Qin Jiahao Feng Xiaotong Feng Wei W. Xing Wang Kang 41 0 0 20 Apr 2025
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Haiyan Qin Zhiwei Xie Jingjing Li Liangchen Li Xiaotong Feng Jun Liu Wang Kang OffRL LRM 191 0 0 20 Apr 2025
SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning Yiting Wang Wanghao Ye Ping Guo Yexiao He Zihan Wang ... Sihan Chen Ankur Srivastava Qingfu Zhang Gang Qu Ang Li 43 0 0 14 Apr 2025
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding Zeng Wang Minghao Shao M. Nabeel P. Roy Likhitha Mankali Jitendra Bhandari Ramesh Karri Ozgur Sinanoglu Muhammad Shafique J. Knechtel 70 0 0 17 Mar 2025
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness Ce Guo Tong Zhao 61 1 0 11 Mar 2025
TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator Deepak Vungarala Mohammed E. Elbtity Sumiya Syed Sakila Alam Kartik Pandit Arnob Ghosh Ramtin Zand Shaahin Angizi 39 1 0 07 Mar 2025
AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies Jian Gao Weidong Cao Junyi Yang Xuan Zhang 44 3 0 28 Feb 2025
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation Reza Moravej Saurabh Bodhe Zhanguang Zhang Didier Chetelat Dimitrios Tsaras Yingxue Zhang Hui-Ling Zhen Jianye Hao M. Yuan 60 1 0 17 Feb 2025
A Survey of Research in Large Language Models for Electronic Design Automation Jingyu Pan Guanglei Zhou Chen-Chia Chang Isaac Jacobson Jiang Hu Yuxiao Chen 74 2 0 17 Jan 2025
Large Language Model Inference Acceleration: A Comprehensive Hardware Perspective Jinhao Li Jiaming Xu Shan Huang Yonghua Chen Wen Li ... Jiayi Pan Li Ding Hao Zhou Yu Wang Guohao Dai 62 16 0 06 Oct 2024
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool Chia-Tung Ho Haoxing Ren Brucek Khailany 49 14 0 15 Aug 2024
VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation Prashanth Vijayaraghavan Luyao Shi S. Ambrogio C. Mackin Apoorva Nitsure David Beymer Ehsan Degan 24 6 0 06 Jun 2024
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust Zeng Wang Lilas Alrahis Likhitha Mankali J. Knechtel Ozgur Sinanoglu 46 9 0 11 May 2024
API Pack: A Massive Multi-Programming Language Dataset for API Call Generation Zhen Guo Adriana Meza Soria Wei Sun Songlin Yang Yikang Shen ELM ALM 55 1 0 14 Feb 2024
Configuration Validation with Large Language Models Xinyu Lian Yinfang Chen Runxiang Cheng Jie Huang Parth Thakkar Minjia Zhang Tianyin Xu 21 10 0 15 Oct 2023
SCAR: Power Side-Channel Analysis at RTL-Level Amisha Srivastava Sanjay Das Navnil Choudhury Rafail Psiakis Pedro Henrique Silva Debjit Pal Kanad Basu 32 8 0 10 Oct 2023
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models Yonggan Fu Yongan Zhang Zhongzhi Yu Sixu Li Zhifan Ye Chaojian Li Cheng Wan Ying Lin 46 61 0 19 Sep 2023
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design Jason Blocklove S. Garg Ramesh Karri Hammond Pearce 45 169 0 22 May 2023
ZeRO-Offload: Democratizing Billion-Scale Model Training Jie Ren Samyam Rajbhandari Reza Yazdani Aminabadi Olatunji Ruwase Shuangyang Yang Minjia Zhang Dong Li Yuxiong He MoE 177 416 0 18 Jan 2021
The Pile: An 800GB Dataset of Diverse Text for Language Modeling Leo Gao Stella Biderman Sid Black Laurence Golding Travis Hoppe ... Horace He Anish Thite Noa Nabeshima Shawn Presser Connor Leahy AIMat 282 2,000 0 31 Dec 2020
Megatron-LM: Training Multi-Billion Parameter Language Models Using Model Parallelism M. Shoeybi M. Patwary Raul Puri P. LeGresley Jared Casper Bryan Catanzaro MoE 245 1,826 0 17 Sep 2019