A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

26 April 2023

Papers citing "A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation"

4 / 4 papers shown

Title
A Survey of Research in Large Language Models for Electronic Design Automation Jingyu Pan Guanglei Zhou Chen-Chia Chang Isaac Jacobson Jiang Hu Y. Chen 71 2 0 17 Jan 2025
BetterV: Controlled Verilog Generation with Discriminative Guidance Zehua Pei Hui-Ling Zhen M. Yuan Yu Huang Bei Yu 32 54 0 03 Feb 2024
CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generation Yue Wang Weishi Wang Shafiq R. Joty S. Hoi 235 1,489 0 02 Sep 2021
The Pile: An 800GB Dataset of Diverse Text for Language Modeling Leo Gao Stella Biderman Sid Black Laurence Golding Travis Hoppe ... Horace He Anish Thite Noa Nabeshima Shawn Presser Connor Leahy AIMat 256 1,996 0 31 Dec 2020