Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO

4 May 2018

Papers citing "Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO"

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Title
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs Pengfei Xu Xiaofan Zhang Cong Hao Yang Katie Zhao Yongan Zhang Yue Wang Chaojian Li Zetong Guan Deming Chen Yingyan Lin 25 89 0 06 Jan 2020
Google's Neural Machine Translation System: Bridging the Gap between Human and Machine Translation Yonghui Wu M. Schuster Zhehuai Chen Quoc V. Le Mohammad Norouzi ... Alex Rudnick Oriol Vinyals G. Corrado Macduff Hughes J. Dean AIMat 718 6,750 0 26 Sep 2016