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VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
v1v2 (latest)

VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

16 May 2025
Patrick Yubeaton
Andre Nakkab
Weihua Xiao
Luca Collini
Ramesh Karri
Chinmay Hegde
Siddharth Garg
    LRM
ArXiv (abs)PDFHTML

Papers citing "VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification"

1 / 1 papers shown
Title
DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning
DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning
DeepSeek-AI
Daya Guo
Dejian Yang
Haowei Zhang
Junxiao Song
...
Shiyu Wang
S. Yu
Shunfeng Zhou
Shuting Pan
S.S. Li
ReLMVLMOffRLAI4TSLRM
384
2,022
0
22 Jan 2025
1