VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at \href{this https URL}{this URL}.

@article{yubeaton2025_2505.20302,
  title={ VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification },
  author={ Patrick Yubeaton and Andre Nakkab and Weihua Xiao and Luca Collini and Ramesh Karri and Chinmay Hegde and Siddharth Garg },
  journal={arXiv preprint arXiv:2505.20302},
  year={ 2025 }
}