AutoVCoder: A Systematic Framework for Automated Verilog Code Generation
using LLMs

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

21 July 2024

Jieru Zhao

Wenchao Ding

Papers citing "AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs"

4 / 4 papers shown

Title
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Haiyan Qin Zhiwei Xie Jingjing Li Liangchen Li Xiaotong Feng Xiaozhong Liu Wang Kang OffRL LRM 167 0 0 20 Apr 2025
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric Bardia Nadimi Ghali Omar Boutaib Hao Zheng 59 1 0 15 Mar 2025
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness Ce Guo Tong Zhao 61 1 0 11 Mar 2025
CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generation Yue Wang Weishi Wang Chenyu You Guosheng Lin 243 1,492 0 02 Sep 2021