Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis

9 May 2024

Papers citing "Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis"

3 / 3 papers shown

Title
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions Yahya Can Tugrul A. Giray Yağlıkçı Ismail Emir Yüksel Ataberk Olgun Oguzhan Canpolat Nisa Bostancı Mohammad Sadrosadati Oguz Ergin O. Mutlu 45 2 0 17 Feb 2025
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips A. G. Yaglikçi Ataberk Olgun Minesh Patel Haocong Luo Hasan Hassan Lois Orosa Oguz Ergin O. Mutlu 32 42 0 21 Sep 2022
SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures Christina Giannoula Nandita Vijaykumar Nikela Papadopoulou Vasileios Karakostas Ivan Fernandez Juan Gómez Luna Lois Orosa N. Koziris G. Goumas O. Mutlu 90 82 0 19 Jan 2021