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A Multi-Expert Large Language Model Architecture for Verilog Code
  Generation

A Multi-Expert Large Language Model Architecture for Verilog Code Generation

11 April 2024
Bardia Nadimi
Hao Zheng
ArXivPDFHTML

Papers citing "A Multi-Expert Large Language Model Architecture for Verilog Code Generation"

6 / 6 papers shown
Title
RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction
RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction
Armin Abdollahi
M. Kamal
Massoud Pedram
MoE
140
1
0
27 Mar 2025
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi
Ghali Omar Boutaib
Hao Zheng
54
1
0
15 Mar 2025
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness
Ce Guo
Tong Zhao
61
1
0
11 Mar 2025
TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator
Deepak Vungarala
Mohammed E. Elbtity
Sumiya Syed
Sakila Alam
Kartik Pandit
Arnob Ghosh
Ramtin Zand
Shaahin Angizi
34
1
0
07 Mar 2025
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
Yonggan Fu
Yongan Zhang
Zhongzhi Yu
Sixu Li
Zhifan Ye
Chaojian Li
Cheng Wan
Ying Lin
46
60
0
19 Sep 2023
Chip-Chat: Challenges and Opportunities in Conversational Hardware
  Design
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove
S. Garg
Ramesh Karri
Hammond Pearce
43
168
0
22 May 2023
1