HDLdebugger: Streamlining HDL debugging with Large Language Models

HDLdebugger: Streamlining HDL debugging with Large Language Models

18 March 2024

Mingxuan Yuan

Papers citing "HDLdebugger: Streamlining HDL debugging with Large Language Models"

8 / 8 papers shown

Title
GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model Wenji Fang Jing Wang Yao Lu Shang Liu Zhiyao Xie AI4CE 39 1 0 13 Apr 2025
Hardware Design and Security Needs Attention: From Survey to Path Forward Sujan Ghimire Muhtasim Alam Chowdhury B. S. Latibari M. Mamun Jaeden Wolf Carpenter Benjamin Tan Hammond Pearce Pratik Satam Soheil Salehi 3DV 48 0 0 11 Apr 2025
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization Xufeng Yao Yiwen Wang Xing Li Yingzhao Lian Ran Chen Lei Chen M. Yuan Hong Xu Bei Yu 37 8 0 04 Sep 2024
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA Zesong Jiang Qing Zhang Cheng Liu Long Cheng Huawei Li Xiaowei Li 47 2 0 17 Jul 2024
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation Kaiyan Chang Zhirong Chen Yunhao Zhou Wenlong Zhu Kun Wang ... Mengdi Wang Shengwen Liang Huawei Li Yinhe Han Ying Wang 48 6 0 11 Jul 2024
Classification-Based Automatic HDL Code Generation Using LLMs Wenhao Sun Bing Li Grace Li Zhang Xunzhao Yin Cheng Zhuo Ulf Schlichtmann 46 2 0 04 Jul 2024
AnalogCoder: Analog Circuit Design via Training-Free Code Generation Yao Lai Sungyoung Lee Guojin Chen Souradip Poddar Mengkang Hu Yao Lai Ping Luo 46 30 0 23 May 2024
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust Zeng Wang Lilas Alrahis Likhitha Mankali J. Knechtel Ozgur Sinanoglu 46 9 0 11 May 2024