Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs

25 August 2023

Papers citing "Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs"

4 / 4 papers shown

Title
Fully integrating the Flang Fortran compiler with standard MLIR Nick Brown LRM 16 1 0 27 Sep 2024
A shared compilation stack for distributed-memory parallelism in stencil DSLs George Bisbas Anton Lydike Emilien Bauer Nick M. Brown Mathieu Fehr ... Gabriel Rodriguez-Canal Maurice Jamieson Paul H. J. Kelly Michel Steuwer Tobias Grosser 35 4 0 02 Apr 2024
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA Gabriel Rodriguez-Canal Nick M. Brown Maurice Jamieson Emilien Bauer Anton Lydike Tobias Grosser 13 3 0 03 Oct 2023
Productivity, Portability, Performance: Data-Centric Python Yiheng Wang Yao Zhang Yanzhang Wang Yan Wan Jiao Wang Zhongyuan Wu Yuhao Yang Bowen She 52 94 0 01 Jul 2021