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Write Me and I'll Tell You Secrets -- Write-After-Write Effects On Intel
  CPUs

Write Me and I'll Tell You Secrets -- Write-After-Write Effects On Intel CPUs

5 September 2022
Jan Philipp Thoma
Tim Güneysu
ArXiv (abs)PDFHTML

Papers citing "Write Me and I'll Tell You Secrets -- Write-After-Write Effects On Intel CPUs"

13 / 13 papers shown
Title
ClepsydraCache -- Preventing Cache Attacks with Time-Based Evictions
ClepsydraCache -- Preventing Cache Attacks with Time-Based Evictions
Jan Philipp Thoma
Christian Niesler
D. Funke
G. Leander
P. Mayr
N. Pohl
Lucas Davi
Tim Güneysu
51
17
0
23 Apr 2021
A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and
  Defenses in Cryptography
A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography
Xiaoxuan Lou
Tianwei Zhang
Jun Jiang
Yinqian Zhang
AAML
51
91
0
26 Mar 2021
Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring
  Interconnect Are Practical
Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical
Riccardo Paccagnella
Licheng Luo
Christopher W. Fletcher
51
106
0
05 Mar 2021
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical
  Fully-Associative Design
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
Gururaj Saileshwar
Moinuddin K. Qureshi
126
84
0
18 Sep 2020
Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel
  Attacks! But We Can Fix It
Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It
Wei Song
Boya Li
Zihan Xue
Zhenzhen Li
Wenhao Wang
Peng Liu
AAML
25
54
0
05 Aug 2020
TurboCC: A Practical Frequency-Based Covert Channel With Intel Turbo
  Boost
TurboCC: A Practical Frequency-Based Covert Channel With Intel Turbo Boost
Manuel Kalmbach
Mathias Gottschlag
T. Schmidt
Frank Bellosa
41
9
0
14 Jul 2020
Store-to-Leak Forwarding: Leaking Data on Meltdown-resistant CPUs
  (Updated and Extended Version)
Store-to-Leak Forwarding: Leaking Data on Meltdown-resistant CPUs (Updated and Extended Version)
Michael Schwarz
Claudio Canella
Lukas Giner
Daniel Gruss
62
45
0
14 May 2019
RELOAD+REFRESH: Abusing Cache Replacement Policies to Perform Stealthy
  Cache Attacks
RELOAD+REFRESH: Abusing Cache Replacement Policies to Perform Stealthy Cache Attacks
Samira Briongos
Pedro Malagón
Jose M. Moya
T. Eisenbarth
54
87
0
12 Apr 2019
A Systematic Evaluation of Transient Execution Attacks and Defenses
A Systematic Evaluation of Transient Execution Attacks and Defenses
Claudio Canella
Jo Van Bulck
Michael Schwarz
Moritz Lipp
Benjamin von Berg
Philipp Ortner
Frank Piessens
Dmitry Evtyushkin
Daniel Gruss
56
408
0
13 Nov 2018
Theory and Practice of Finding Eviction Sets
Theory and Practice of Finding Eviction Sets
Pepe Vila
Boris Köpf
J. Morales
39
130
0
02 Oct 2018
Spectre Attacks: Exploiting Speculative Execution
Spectre Attacks: Exploiting Speculative Execution
P. Kocher
Daniel Genkin
Daniel Gruss
Werner Haas
Michael Hamburg
Moritz Lipp
Stefan Mangard
Thomas Prescher
Michael Schwarz
Y. Yarom
SILM
76
2,187
0
03 Jan 2018
DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks
DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks
P. Pessl
Daniel Gruss
Clémentine Maurice
Michael Schwarz
Stefan Mangard
56
453
0
27 Nov 2015
Flush+Flush: A Fast and Stealthy Cache Attack
Flush+Flush: A Fast and Stealthy Cache Attack
Daniel Gruss
Clémentine Maurice
Klaus Wagner
Stefan Mangard
80
581
0
14 Nov 2015
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