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A Security-aware and LUT-based CAD Flow for the Physical Synthesis of
  eASICs

A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs

12 July 2022
Zain Ul Abideen
T. Perez
Mayler G. A. Martins
S. Pagliarini
ArXiv (abs)PDFHTML

Papers citing "A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs"

2 / 2 papers shown
Title
FuncTeller: How Well Does eFPGA Hide Functionality?
FuncTeller: How Well Does eFPGA Hide Functionality?
Zhaokun Han
Mohammed Shayan
Aneesh Dixit
M. Shihab
Yiorgos Makris
Jeyavijayan Rajendran
44
7
0
08 Jun 2023
An Overview of FPGA-inspired Obfuscation Techniques
An Overview of FPGA-inspired Obfuscation Techniques
Zain Ul Abideen
S. Gokulanathan
Muayad J. Aljafar
S. Pagliarini
AAML
42
3
0
25 May 2023
1