From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

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From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

11 October 2021

Zain Ul Abideen

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Papers citing "From FPGAs to Obfuscated eASICs: Design and Security Trade-offs"

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Title
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Luca Collini Jitendra Bhandari Chiara Muscari Tomajoli Abdul Khader Thalakkattu Moosa Benjamin Tan Xifan Tang P. Gaillardon Ramesh Karri C. Pilato 54 0 0 01 Jun 2025
An Overview of FPGA-inspired Obfuscation Techniques Zain Ul Abideen S. Gokulanathan Muayad J. Aljafar S. Pagliarini AAML 42 3 0 25 May 2023
High-Level Approaches to Hardware Security: A Tutorial Hammond Pearce Ramesh Karri Benjamin Tan 36 7 0 21 Jul 2022
A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs Zain Ul Abideen T. Perez Mayler G. A. Martins S. Pagliarini 28 8 0 12 Jul 2022