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Reconfigurable Low-latency Memory System for Sparse Matricized Tensor
  Times Khatri-Rao Product on FPGA

Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA

18 September 2021
Sasindu Wijeratne
R. Kannan
Viktor Prasanna
ArXivPDFHTML

Papers citing "Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA"

2 / 2 papers shown
Title
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory
Ruizhi Zhang
Sasindu Wijeratne
Yang Yang
S. Kuppannagari
Viktor Prasanna
11
5
0
07 Aug 2021
Tensor Decomposition for Signal Processing and Machine Learning
Tensor Decomposition for Signal Processing and Machine Learning
N. Sidiropoulos
L. De Lathauwer
Xiao Fu
Kejun Huang
Evangelos E. Papalexakis
Christos Faloutsos
105
1,342
0
06 Jul 2016
1