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Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication

G. Moon
Hyoukjun Kwon
Geonhwa Jeong
Prasanth Chatarasi
S. Rajamanickam
T. Krishna
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Papers citing "Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication"

2 / 2 papers shown
Title
Seculator: A Fast and Secure Neural Processing Unit
Seculator: A Fast and Secure Neural Processing Unit
Nivedita Shrivastava
S. Sarangi
AAML
31
3
0
19 Apr 2022
Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators
Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators
Geonhwa Jeong
Gokcen Kestor
Prasanth Chatarasi
A. Parashar
Po-An Tsai
S. Rajamanickam
R. Gioiosa
T. Krishna
35
13
0
15 Sep 2021