Abusing Cache Line Dirty States to Leak Information in Commercial
Processors

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Abusing Cache Line Dirty States to Leak Information in Commercial Processors

17 April 2021

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Papers citing "Abusing Cache Line Dirty States to Leak Information in Commercial Processors"

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Title
Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It Wei Song Boya Li Zihan Xue Zhenzhen Li Wenhao Wang Peng Liu AAML 31 54 0 05 Aug 2020
Survey of Transient Execution Attacks Wenjie Xiong Jakub Szefer SILM 73 25 0 27 May 2020
Leaking Information Through Cache LRU States Wenjie Xiong Jakub Szefer 64 70 0 20 May 2019
RELOAD+REFRESH: Abusing Cache Replacement Policies to Perform Stealthy Cache Attacks Samira Briongos Pedro Malagón Jose M. Moya T. Eisenbarth 57 87 0 12 Apr 2019
SMoTherSpectre: exploiting speculative execution through port contention Atri Bhattacharyya A. Sandulescu M. Neugschwandtner A. Sorniotti Babak Falsafi Mathias Payer Anil Kurmus 52 243 0 05 Mar 2019
Spectre Attacks: Exploiting Speculative Execution P. Kocher Daniel Genkin Daniel Gruss Werner Haas Michael Hamburg Moritz Lipp Stefan Mangard Thomas Prescher Michael Schwarz Y. Yarom SILM 87 2,190 0 03 Jan 2018
MemJam: A False Dependency Attack against Constant-Time Crypto Implementations A. Moghimi T. Eisenbarth B. Sunar 48 81 0 21 Nov 2017
Flush+Flush: A Fast and Stealthy Cache Attack Daniel Gruss Clémentine Maurice Klaus Wagner Stefan Mangard 101 581 0 14 Nov 2015