Timing Cache Accesses to Eliminate Side Channels in Shared Software

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Timing Cache Accesses to Eliminate Side Channels in Shared Software

30 September 2020

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Papers citing "Timing Cache Accesses to Eliminate Side Channels in Shared Software"

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Title
Leaking Information Through Cache LRU States Wenjie Xiong Jakub Szefer 61 70 0 20 May 2019
NetSpectre: Read Arbitrary Memory over Network Michael Schwarz Martin Schwarzl Moritz Lipp Daniel Gruss 40 232 0 27 Jul 2018
Spectre Returns! Speculation Attacks using the Return Stack Buffer Esmaeil Mohammadian Koruyeh Khaled N. Khasawneh Chengyu Song Nael B. Abu-Ghazaleh SILM AAML 46 190 0 20 Jul 2018
SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation Khaled N. Khasawneh Esmaeil Mohammadian Koruyeh Chengyu Song Dmitry Evtyushkin D. Ponomarev Nael B. Abu-Ghazaleh 58 183 0 13 Jun 2018
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks Charles Eckert Xiaowei Wang Jingcheng Wang Arun K. Subramaniyan R. Iyer D. Sylvester D. Blaauw R. Das MQ 48 341 0 09 May 2018
Spectre Attacks: Exploiting Speculative Execution P. Kocher Daniel Genkin Daniel Gruss Werner Haas Michael Hamburg Moritz Lipp Stefan Mangard Thomas Prescher Michael Schwarz Y. Yarom SILM 79 2,189 0 03 Jan 2018
Flush+Flush: A Fast and Stealthy Cache Attack Daniel Gruss Clémentine Maurice Klaus Wagner Stefan Mangard 80 581 0 14 Nov 2015