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FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence
  on the Edge

FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge

9 April 2019
Cong Hao
Xiaofan Zhang
Yuhong Li
Sitao Huang
Jinjun Xiong
K. Rupnow
Wen-mei W. Hwu
Deming Chen
ArXivPDFHTML

Papers citing "FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge"

32 / 32 papers shown
Title
Moss: Proxy Model-based Full-Weight Aggregation in Federated Learning with Heterogeneous Models
Y. Cai
Ziqi Zhang
Ding Li
Yao Guo
Xiangqun Chen
55
0
0
13 Mar 2025
A High-Performance Accelerator for Super-Resolution Processing on
  Embedded GPU
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU
W. Zhao
Qi Sun
Yang Bai
Wenbo Li
Haisheng Zheng
Bei Yu
Martin D. F. Wong
SupR
44
8
0
16 Mar 2023
TinyAD: Memory-efficient anomaly detection for time series data in
  Industrial IoT
TinyAD: Memory-efficient anomaly detection for time series data in Industrial IoT
Yuting Sun
Tong Chen
Quoc Viet Hung Nguyen
Hongzhi Yin
23
12
0
07 Mar 2023
Enabling Hard Constraints in Differentiable Neural Network and
  Accelerator Co-Exploration
Enabling Hard Constraints in Differentiable Neural Network and Accelerator Co-Exploration
Deokki Hong
Kanghyun Choi
Hyeyoon Lee
Joonsang Yu
Noseong Park
Youngsok Kim
Jinho Lee
19
3
0
23 Jan 2023
Theta-Resonance: A Single-Step Reinforcement Learning Method for Design
  Space Exploration
Theta-Resonance: A Single-Step Reinforcement Learning Method for Design Space Exploration
Masood S. Mortazavi
Tiancheng Qin
Ning Yan
25
2
0
03 Nov 2022
PolyMPCNet: Towards ReLU-free Neural Architecture Search in Two-party Computation Based Private Inference
Hongwu Peng
Shangli Zhou
Yukui Luo
Shijin Duan
Nuo Xu
...
Tong Geng
Ang Li
Wujie Wen
Xiaolin Xu
Caiwen Ding
35
3
0
20 Sep 2022
EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data
  Reshaping for Online Adaptation or Personalization
EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalization
Yue Tang
Xinyi Zhang
Peipei Zhou
Jingtong Hu
21
17
0
18 Feb 2022
EH-DNAS: End-to-End Hardware-aware Differentiable Neural Architecture
  Search
EH-DNAS: End-to-End Hardware-aware Differentiable Neural Architecture Search
Qian Jiang
Xiaofan Zhang
Deming Chen
Minh Do
Raymond A. Yeh
27
7
0
24 Nov 2021
RT-RCG: Neural Network and Accelerator Search Towards Effective and
  Real-time ECG Reconstruction from Intracardiac Electrograms
RT-RCG: Neural Network and Accelerator Search Towards Effective and Real-time ECG Reconstruction from Intracardiac Electrograms
Yongan Zhang
Anton Banta
Yonggan Fu
M. John
A. Post
M. Razavi
Joseph R. Cavallaro
B. Aazhang
Yingyan Lin
26
4
0
04 Nov 2021
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN
  Accelerators for Edge Inference
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference
Jude Haris
Perry Gibson
José Cano
Nicolas Bohm Agostini
David Kaeli
44
19
0
01 Oct 2021
G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and
  Efficiency
G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and Efficiency
Yongan Zhang
Haoran You
Yonggan Fu
Tong Geng
Ang Li
Yingyan Lin
GNN
21
28
0
18 Sep 2021
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory
Ruizhi Zhang
Sasindu Wijeratne
Yang Yang
S. Kuppannagari
Viktor Prasanna
22
5
0
07 Aug 2021
A3C-S: Automated Agent Accelerator Co-Search towards Efficient Deep Reinforcement Learning
A3C-S: Automated Agent Accelerator Co-Search towards Efficient Deep Reinforcement Learning
Yonggan Fu
Yongan Zhang
Chaojian Li
Zhongzhi Yu
Yingyan Lin
37
6
0
11 Jun 2021
NAAS: Neural Accelerator Architecture Search
NAAS: Neural Accelerator Architecture Search
Yujun Lin
Mengtian Yang
Song Han
31
59
0
27 May 2021
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low BitwidthQuantization,
  and Ultra-Low Latency Acceleration
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low BitwidthQuantization, and Ultra-Low Latency Acceleration
Yao Chen
Cole Hawkins
Kaiqi Zhang
Zheng-Wei Zhang
Cong Hao
26
8
0
11 May 2021
HAO: Hardware-aware neural Architecture Optimization for Efficient
  Inference
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
Zhen Dong
Yizhao Gao
Qijing Huang
J. Wawrzynek
Hayden Kwok-Hay So
Kurt Keutzer
19
34
0
26 Apr 2021
Enabling Design Methodologies and Future Trends for Edge AI:
  Specialization and Co-design
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design
Cong Hao
Jordan Dotzel
Jinjun Xiong
Luca Benini
Zhiru Zhang
Deming Chen
58
34
0
25 Mar 2021
HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural
  Architecture Search
HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search
Xiangzhong Luo
Di Liu
Shuo Huai
Weichen Liu
20
6
0
11 Mar 2021
A Comprehensive Survey on Hardware-Aware Neural Architecture Search
A Comprehensive Survey on Hardware-Aware Neural Architecture Search
Hadjer Benmeziane
Kaoutar El Maghraoui
Hamza Ouarnoughi
Smail Niar
Martin Wistuba
Naigang Wang
34
96
0
22 Jan 2021
DNA: Differentiable Network-Accelerator Co-Search
DNA: Differentiable Network-Accelerator Co-Search
Yongan Zhang
Y. Fu
Weiwen Jiang
Chaojian Li
Haoran You
Meng Li
Vikas Chandra
Yingyan Lin
28
17
0
28 Oct 2020
Standing on the Shoulders of Giants: Hardware and Neural Architecture
  Co-Search with Hot Start
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search with Hot Start
Weiwen Jiang
Lei Yang
Sakyasingha Dasgupta
Jiaxi Hu
Yiyu Shi
27
59
0
17 Jul 2020
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML
  Models: A Survey and Insights
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights
Shail Dave
Riyadh Baghdadi
Tony Nowatzki
Sasikanth Avancha
Aviral Shrivastava
Baoxin Li
59
82
0
02 Jul 2020
EDD: Efficient Differentiable DNN Architecture and Implementation
  Co-search for Embedded AI Solutions
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
Yuhong Li
Cong Hao
Xiaofan Zhang
Xinheng Liu
Yao Chen
Jinjun Xiong
Wen-mei W. Hwu
Deming Chen
34
77
0
06 May 2020
DNN-Chip Predictor: An Analytical Performance Predictor for DNN
  Accelerators with Various Dataflows and Hardware Architectures
DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures
Yang Katie Zhao
Chaojian Li
Yue Wang
Pengfei Xu
Yongan Zhang
Yingyan Lin
25
41
0
26 Feb 2020
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware
  Accelerator
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator
Mohamed S. Abdelfattah
L. Dudziak
Thomas C. P. Chau
Royson Lee
Hyeji Kim
Nicholas D. Lane
17
79
0
11 Feb 2020
Co-Exploration of Neural Architectures and Heterogeneous ASIC
  Accelerator Designs Targeting Multiple Tasks
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Lei Yang
Zheyu Yan
Meng Li
Hyoukjun Kwon
Liangzhen Lai
T. Krishna
Vikas Chandra
Weiwen Jiang
Yiyu Shi
23
114
0
10 Feb 2020
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs
  and ASICs
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
Pengfei Xu
Xiaofan Zhang
Cong Hao
Yang Katie Zhao
Yongan Zhang
Yue Wang
Chaojian Li
Zetong Guan
Deming Chen
Yingyan Lin
25
88
0
06 Jan 2020
NAIS: Neural Architecture and Implementation Search and its Applications
  in Autonomous Driving
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
Cong Hao
Yao Chen
Xinheng Liu
A. Sarwari
Daryl Sew
...
Dongdong Fu
Jinjun Xiong
Wen-mei W. Hwu
Junli Gu
Deming Chen
3DV
16
21
0
18 Nov 2019
2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping
  of Deep Learning Architecture (DLA) onto FPGA Boards
2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Deep Learning Architecture (DLA) onto FPGA Boards
Tolulope A. Odetola
Katie M. Groves
S. R. Hasan
29
5
0
14 Nov 2019
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory
  Neural Accelerators
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Weiwen Jiang
Qiuwen Lou
Zheyu Yan
Lei Yang
Jiaxi Hu
X. S. Hu
Yiyu Shi
11
71
0
31 Oct 2019
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on
  Embedded Systems
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems
Xiaofan Zhang
Haoming Lu
Cong Hao
Jiachen Li
Bowen Cheng
...
Jinjun Xiong
Thomas Huang
Humphrey Shi
Wen-mei W. Hwu
Deming Chen
39
92
0
20 Sep 2019
Neural Architecture Search with Reinforcement Learning
Neural Architecture Search with Reinforcement Learning
Barret Zoph
Quoc V. Le
271
5,327
0
05 Nov 2016
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