ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and
Data Organization for Deep Neural Network Accelerators

v1v2 (latest)

ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

4 February 2019

Rachmad Vidya Wicaksana Putra

Muhammad Abdullah Hanif

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Papers citing "ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators"

7 / 7 papers shown

Title
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead Maurizio Capra Beatrice Bussolino Alberto Marchisio Guido Masera Maurizio Martina Mohamed Bennai BDL 100 145 0 21 Dec 2020
AMC: AutoML for Model Compression and Acceleration on Mobile Devices Yihui He Ji Lin Zhijian Liu Hanrui Wang Li Li Song Han 98 1,349 0 10 Feb 2018
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks Hardik Sharma Jongse Park Naveen Suda Liangzhen Lai Benson Chau Joo-Young Kim Vikas Chandra H. Esmaeilzadeh MQ 61 492 0 05 Dec 2017
In-Datacenter Performance Analysis of a Tensor Processing Unit N. Jouppi C. Young Nishant Patil David Patterson Gaurav Agrawal ... Vijay Vasudevan Richard Walter Walter Wang Eric Wilcox Doe Hyun Yoon 237 4,644 0 16 Apr 2017
Efficient Processing of Deep Neural Networks: A Tutorial and Survey Vivienne Sze Yu-hsin Chen Tien-Ju Yang J. Emer AAML 3DV 120 3,026 0 27 Mar 2017
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size F. Iandola Song Han Matthew W. Moskewicz Khalid Ashraf W. Dally Kurt Keutzer 156 7,501 0 24 Feb 2016
Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding Song Han Huizi Mao W. Dally 3DGS 263 8,859 0 01 Oct 2015

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