Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout
Camouflaging

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Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

14 November 2017

Ozgur Sinanoglu

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Papers citing "Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging"

7 / 7 papers shown

Title
Complexity Analysis of the SAT Attack on Logic Locking Yadi Zhong Ujjwal Guin 52 16 0 05 Jul 2022
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques Arunkumar Vijayakumar Vinay C. Patil Daniel E. Holcomb C. Paar S. Kundu 25 80 0 02 Oct 2019
Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL Satwik Patnaik M. Ashraf J. Knechtel Ozgur Sinanoglu 39 18 0 24 Jun 2018
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing Satwik Patnaik J. Knechtel M. Ashraf Ozgur Sinanoglu 48 23 0 03 Jun 2018
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques A. Sengupta Satwik Patnaik J. Knechtel M. Ashraf S. Garg Ozgur Sinanoglu 48 25 0 05 Oct 2017
Design Automation for Obfuscated Circuits with Multiple Viable Functions S. Keshavarz C. Paar Daniel E. Holcomb 31 9 0 01 Mar 2017
Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks M. Collantes Mohamed El Massad S. Garg 25 40 0 02 May 2016