ResearchTrend.AI
  • Papers
  • Communities
  • Events
  • Blog
  • Pricing
Papers
Communities
Social Events
Terms and Conditions
Pricing
Parameter LabParameter LabTwitterGitHubLinkedInBlueskyYoutube

© 2025 ResearchTrend.AI, All rights reserved.

  1. Home
  2. Papers
  3. 1704.00693
  4. Cited By
Loop Tiling in Large-Scale Stencil Codes at Run-time with OPS
v1v2 (latest)

Loop Tiling in Large-Scale Stencil Codes at Run-time with OPS

3 April 2017
I. Reguly
G. Mudalige
M. Giles
ArXiv (abs)PDFHTML

Papers citing "Loop Tiling in Large-Scale Stencil Codes at Run-time with OPS"

8 / 8 papers shown
Title
Scheduling Languages: A Past, Present, and Future Taxonomy
Scheduling Languages: A Past, Present, and Future Taxonomy
Mary Hall
Cosmin Oancea
Anne C. Elster
Ari Rasch
Sameeran Joshi
Amir Mohammad Tavakkoli
Richard Schulze
75
1
0
25 Oct 2024
A shared compilation stack for distributed-memory parallelism in stencil
  DSLs
A shared compilation stack for distributed-memory parallelism in stencil DSLs
George Bisbas
Anton Lydike
Emilien Bauer
Nick M. Brown
Mathieu Fehr
...
Gabriel Rodriguez-Canal
Maurice Jamieson
Paul H. J. Kelly
Michel Steuwer
Tobias Grosser
119
4
0
02 Apr 2024
Comparative evaluation of bandwidth-bound applications on the Intel Xeon
  CPU MAX Series
Comparative evaluation of bandwidth-bound applications on the Intel Xeon CPU MAX Series
I. Reguly
20
4
0
16 Sep 2023
A Synergy between On- and Off-Chip Data Reuse for GPU-based Out-of-Core
  Stencil Computation
A Synergy between On- and Off-Chip Data Reuse for GPU-based Out-of-Core Stencil Computation
Jingcheng Shen
Linbo Long
Jun Zhang
Weiqi Shen
M. Okita
Fumihiko Ino
19
0
0
16 Sep 2023
Breaking the Computation and Communication Abstraction Barrier in
  Distributed Machine Learning Workloads
Breaking the Computation and Communication Abstraction Barrier in Distributed Machine Learning Workloads
Abhinav Jangda
Jun Huang
Guodong Liu
Amir Hossein Nodehi Sabet
Saeed Maleki
Youshan Miao
Madan Musuvathi
Todd Mytkowicz
Olli Saarikivi
77
64
0
12 May 2021
High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit
  Numerical Solvers
High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers
Kamalavasan Kamalakkannan
G. Mudalige
I. Reguly
Suhaib A. Fahmy
53
8
0
04 Jan 2021
High-Performance Code Generation though Fusion and Vectorization
High-Performance Code Generation though Fusion and Vectorization
J. Sewall
S. Pennycook
30
2
0
24 Oct 2017
Beyond 16GB: Out-of-Core Stencil Computations
Beyond 16GB: Out-of-Core Stencil Computations
I. Reguly
G. Mudalige
M. Giles
34
9
0
07 Sep 2017
1