Multi-dimensional intra-tile parallelization for memory-starved stencil
computations

Multi-dimensional intra-tile parallelization for memory-starved stencil computations

16 October 2015

Hatem Ltaief

ArXiv (abs)PDF HTML

Papers citing "Multi-dimensional intra-tile parallelization for memory-starved stencil computations"

7 / 7 papers shown

Title
Optimization of an electromagnetics code with multicore wavefront diamond blocking and multi-dimensional intra-tile parallelization T. Malas Julian Hornich G. Hager Hatem Ltaief C. Pflaum David E. Keyes 53 16 0 18 Oct 2015
Performance analysis of the Kahan-enhanced scalar product on current multicore processors Johannes Hofmann D. Fey Jan Eitzinger G. Hager G. Wellein 43 11 0 11 May 2015
Quantifying performance bottlenecks of stencil computations using the Execution-Cache-Memory model H. Stengel Jan Treibig G. Hager G. Wellein 43 116 0 18 Oct 2014
Multicore-optimized wavefront diamond blocking for optimizing stencil updates T. Malas G. Hager Hatem Ltaief H. Stengel G. Wellein David E. Keyes 31 76 0 12 Oct 2014
Exploring performance and power properties of modern multicore chips via simple machine models G. Hager Jan Treibig J. Habich G. Wellein 61 114 0 14 Aug 2012
Leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters M. Wittmann G. Hager Jan Treibig G. Wellein 82 26 0 16 Jun 2010
Efficient multicore-aware parallelization strategies for iterative stencil computations Jan Treibig G. Wellein G. Hager 46 62 0 10 Apr 2010