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Quantifying performance bottlenecks of stencil computations using the Execution-Cache-Memory model
18 October 2014
H. Stengel
Jan Treibig
G. Hager
G. Wellein
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Papers citing
"Quantifying performance bottlenecks of stencil computations using the Execution-Cache-Memory model"
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Title
Exploring performance and power properties of modern multicore chips via simple machine models
G. Hager
Jan Treibig
J. Habich
G. Wellein
63
114
0
14 Aug 2012
1
