Large Language Models (LLMs) offer transformative capabilities for hardware design automation, particularly in Verilog code generation. However, they also pose significant data security challenges, including Verilog evaluation data contamination, intellectual property (IP) design leakage, and the risk of malicious Verilog generation. We introduce SALAD, a comprehensive assessment that leverages machine unlearning to mitigate these threats. Our approach enables the selective removal of contaminated benchmarks, sensitive IP and design artifacts, or malicious code patterns from pre-trained LLMs, all without requiring full retraining. Through detailed case studies, we demonstrate how machine unlearning techniques effectively reduce data security risks in LLM-aided hardware design.
View on arXiv@article{wang2025_2506.02089,
title={ SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design },
author={ Zeng Wang and Minghao Shao and Rupesh Karn and Likhitha Mankali and Jitendra Bhandari and Ramesh Karri and Ozgur Sinanoglu and Muhammad Shafique and Johann Knechtel },
journal={arXiv preprint arXiv:2506.02089},
year={ 2025 }
}