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Hypersparse Traffic Matrix Construction using GraphBLAS on a DPU

20 October 2023
William Bergeron
Michael Jones
Chase Barber
Kale DeYoung
G. Amariucai
Kaleb Ernst
Nathan Fleming
Peter Michaleas
Sandeep Pisharody
Nathan Wells
Antonio Rosa
Eugene Y. Vasserman
J. Kepner
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Abstract

Low-power small form factor data processing units (DPUs) enable offloading and acceleration of a broad range of networking and security services. DPUs have accelerated the transition to programmable networking by enabling the replacement of FPGAs/ASICs in a wide range of network oriented devices. The GraphBLAS sparse matrix graph open standard math library is well-suited for constructing anonymized hypersparse traffic matrices of network traffic which can enable a wide range of network analytics. This paper measures the performance of the GraphBLAS on an ARM based NVIDIA DPU (BlueField 2) and, to the best of our knowledge, represents the first reported GraphBLAS results on a DPU and/or ARM based system. Anonymized hypersparse traffic matrices were constructed at a rate of over 18 million packets per second.

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